The present disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a semiconductor device including a multi-layered, pillar type storage node and a method of fabricating the semiconductor device.
Recently, as memory devices have been highly integrated by a miniaturized semiconductor processing technology, which is rapidly developing, an area of a unit cell is significantly decreased and low voltage is used as an operating voltage. However, although the cell area has been decreasing, it is beneficial to keep the required charge capacitance in the operation of the memory device larger than 25 fF/cell to prevent the shortening of a refresh time and the generation of a soft error.
Under these circumstances, a metal insulator metal (MIM) type capacitor employing a high-k dielectric layer to secure charge capacitance required in the next generation DRAM devices is being developed. Such a capacitor uses TiN or Ru to form a storage node. Furthermore, in a semiconductor DRAM product line employing a metallization technology of less than 50 nm, an effective cell area is substantially reduced, a capacitor of the cell is formed with a storage node structure having a shape such as a circle, an ellipse or oval, or a pillar.
However, when increasing a height of the storage node having a pillar shape to obtain much higher charge capacitance, a leaning phenomenon occurs between adjacent storage nodes as illustrated in FIG. 1 and thus an electrical defect may occur.
FIG. 1 is an image showing a leaning phenomenon of a storage node in the prior art. Referring to FIG. 1, there is a bridge between adjacent storage nodes since storage nodes are leaned towards each other or even together such that they are touching.